Low-power LFSR Kernel Architecture in Mobile Transmitter and Receiver Protocols and Software Defined Radios

The LFSR operations are performed in implementing the different mobile-device protocols and encryption standards during transmission and reception. These operations are performed at the PN coding stages in CDMA, Gold code generation stage in WCDMA and several operation stages in the mobile transmitter and receiver protocols in Software Defined Radios (SDRs). A kernel can instantiate several processing objects when processing in the processor. Use of the kernel is known to lead to reduced energy dissipation by reducing the need of just a few memory accesses. A kernel for the multi-bit output Linear Feedback Shift Register (LFSR) operations is proposed in this paper. An Instruction Set Architecture (ISA) proposed for the kernel gives the functional instantiation at the stages of generation of PN long sequence, PNI short sequence and PNQ short sequence, Msequence, Gold code sequence, CRC sequence and Signature sequence in the SDR link-applications, and other wireless applications. The paper also gives the results of computations of dynamic power consumption (DPC) in the kernel architecture. The estimation of required number of memory accesses of the kernel based upon the proposed ISA is also given in the paper. The LFSR kernel is shown to need just a few memory accesses, thus significantly reducing the power requirement in comparison to the software implementation of the above stages.